I'm Steffen Vogel

Computer Engineer

  • Age 26
  • Born in Baden, Switzerland
  • Raised around Darmstadt, Germany
  • Living now in Aachen, Germany
  • E-mail post@steffenvogel.de
  • Phone +49 1575 7180927
  • Languages learned English, Korean, Basic, C, C++, JS, PHP, Java, VHDL, Tcl, Assembly, SQL, Bash, Erlang, Go
  • Living in Montreal till December, 2016

About Me

Welcome to my personal website! My name is Steffen Vogel, I am a German EECS student at the RWTH Aachen University with interests in reconfigurable & high performance computing and their application in the fields of real-time simulation.

On this site you can find my extended resumé, contact information as well as my contributions to various open source projects and scientific publications.

In 2007, I started my blog at noteblok.net. It is my personal notebook for various tech and work related bits like my open-source and electronics projects.

In order to contact me, you can leave a message in the contact form below, send me a mail or use one of the social media sites linked on my Keybase.io account.

Professional Skills

C / C++
Matlab / Simulink
Xilinx Vivado / ISE / XPS / HLS
MPI & OpenMP

My Tools


Hardware Projects



A fnordlicht compatible controller for LED strips

A self-made LED matrix for TETRIS


RWTH Mikrocontroller Board

Camera-based Solder Paste Dispensing


St Petersburg

Photography Travelling

Work Experience

05.2017 - ?

Research Assistant: Doctoral Candidate

Institute for Automation of Complex Power Systems, RWTH Aachen University

Starting a Ph.D. in the ICT4Energy team of the Institute.
Advisor: Prof. Dr.-Ing. Antonello Monti

08.2016 - 01.2017


OPAL-RT Technologies Inc.

During this five month-long internship in OPAL-RT's eFPGAsim team, I worked extensively with MATLAB Simulink and Xilinx tools to implement FPGA-based solvers for power electronics simulation.

04.2014 – 07.2016

Science Assistant: Internet distributed power grid simulation

Institute for Automation of Complex Power Systems, RWTH Aachen University

Implementing real-time communication tools based on RT-Linux, OPAL-RT and RTDS simulators. Supervisor: M.Sc. Marija Stevic

04.2014 – 08.2014

Exercise Instructor: Hands-on sessions computer science 4

Chair for Operating Systems, RWTH Aachen University

Undertaking exercises on system / parallel programming, x86-Assembly and more

10.2011 – 04.2012

Student Tutor: C / C++ programming laboratory

Institute for Man- Machine Interaction, RWTH Aachen University

Supervising and examination a practical course on C / C++ programming

09.2011 – 08.2013

Student Lecturer: Micro controller study group

Institute for Man- Machine Interaction, RWTH Aachen University

Giving introductory lectures on micro controller programming based on the Atmel ATmega family.

Former employers


10.2014 – Present

M.Sc. Electrical Engineering, Information Technology and Computer Engineering

RWTH University, Aachen

10.2010 – 10.2014

B.Sc. Electrical Engineering, Information Technology and Computer Engineering

RWTH University, Aachen

08.2001 – 06.2009


Justus-Liebig-Schule (Gymnasium)



[4] Steffen Vogel. Development of a modular and fully-digital PCIe-based interface to Real-Time Digital Simulator. Master Thesis, Grade: A+. RWTH Aachen University. To be submitted, August 2016.

[3] Steffen Vogel. Image processing and content analysis camera-based PCB analysis for solder paste dispensing. Seminar: Image Processing and Content Analysis. Institute of Imaging & Computer Vision, RWTH Aachen University, February 2015.

[2] Steffen Vogel. Self-referencing Page Tables for the x86-Architecture – A simple Paging Implementation for a minimalistic Operating System. Submission for ASPLOS Student Research Competition. Istanbul, Turkey, December 2014.

[1] Steffen Vogel. A generic memory management with paging for a minimalistic operating system. Bachelor Thesis, Grade: A+. RWTH Aachen University, Chair for Operating Systems, June 2014.


[3] E. Bompard et. al. A multi-site real-time co-simulation platform for the testing of control strategies of distributed storage and V2G in distribution networks, September 2016

[2] JRC-IET, Politecnico di Torino, RWTH Aachen University. A European Platform for Distributed Real Time Modelling & Simulation of Emerging Electricity Systems. JRC Technical Report, Mai 2016.

[1] Marija Stevic, Steffen Vogel, Antonello Monti, and Salvatore D’Arco. Feasibility of geographically distributed real-time simulation of HVDC system interconnected with AC networks. IEEE Power Tech, Eindhoven, June 2015.

Contact Me

Feel free to contact me